1. Field of the Invention
The present invention relates to a method and apparatus for reporting a status of a device connected to a second bus that is connected, through a bridge, to a first bus to which a central processing unit and a storage unit are connected, with a capability of improving the usability of the second bus by eliminating the nonessential use of the second bus.
2. Description of the Related Art
In conventional technology, when a central processing unit (CPU) connected to a host bus (first bus) acquires a status of a device connected to a peripheral component interconnect (PCI) bus (second bus) that is connected to the host bus via a bridge, the CPU polls the status of the device.
FIG. 8 is a diagram for explaining a conventional device status reporting system. When a CPU 10 acquires, through a bridge 40, a status of a device C 800 that is connected to a PCI bus 50, the CPU 10 reads a status register 810 of the device C 800 through a host bus 30, the bridge 40, and the PCI bus 50. The technology in which the CPU reads the status of the device by polling is disclosed in Japanese Patent Application Laid-Open No. S59-122257.
Instead of the CPU 10 that polls the device C 800, the device C 800 writes the status to a memory 20 using a direct memory access (DMA) function and the CPU 10 reads the memory 20, thereby acquiring the status of the device C 800. The technologies for writing a device status to a memory using the DMA function is disclosed in, for example, Japanese Patent Application Laid-Open No. S57-103530, Japanese Patent Application Laid-Open No. 2001-45095, and Japanese Patent Application Laid-Open No. H09-204311.
In the case of a polling system, however, reading the status from the status register 810 is performed through the PCI bus 50 ((1) of FIG. 8), and in the case of a DMA system, writing the status to the memory 20 is performed through the PCI bus 50 ((2) of FIG. 8). Therefore, if an event of polling or DMA occurs during data transfer ((3) of FIG. 8) from a device A 60 to a device B 70, both of which are connected to the PCI bus 50, the data transfer is interrupted each time the event occurs, which leads to deterioration in data transfer efficiency of the PCI bus 50.